Memory devices are used in all fields of data processing technology to store various kinds of data. A memory device may be shared among several clients. As the total data rate or bandwidth for transferring data to or from the memory device is limited, a scheme may be needed to control the access of each individual client to the memory device so as to avoid interference between simultaneous access attempts by different clients. Such scheme may be implemented by means of a memory arbiter. The arbiter receives memory access requests from the various clients and grants access to the memory device in accordance with some suitable rule. The rule may take into account criteria such as the time at which a particular request was generated, the amount of data to be transferred to or from the respective client and the urgency of the request. The memory arbiter, in response to a request received from one of the clients, may for example allocate a certain data rate or bandwidth for that particular client, and deallocate the reserved data rate or bandwidth in response to a signal from that client or in response to some other triggering event, for example upon completion of a task executed by that client.
A data rate is a number of transferred bits per second. A data rate is equivalent to a bandwidth of a signal used to transfer the data.
U.S. Pat. No. 4,953,103 (Suzuki) describes a page printer comprising a central processing unit (CPU), internal memories, and a direct memory access controller (DMAC) for transferring data to or from a memory at high speed without requiring intervention by the CPU. The CPU, DMAC, and memories are interconnected by a bus over which data can be transferred. During a direct memory access (DMA) operation the bus is controlled by the DMAC and cannot be used by the CPU. In order to ensure that the CPU is not disabled for extended periods of time by long DMA operations, the page printer comprises a DMA stopping circuit for stopping and restarting DMA transfers in response to certain interrupt request signals received by the CPU. Access of the DMAC to the bus is thus controlled directly by means of interrupt request signals.